This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In modern circuit design, memory and related mechanisms support dual voltage rails for bitcell core (VDDCE) and periphery circuitry (VDDPE). VDDCE lowering is limited by bitcell retention voltage and is held at higher voltages compared to VDDPE. However, VDDPE lowering is usually limited by internal circuitry. Typically, VDDPE may potentially limit power savings on chip. Large range level shifting may require level shift of all inputs inside memory from low VDDPE to higher VDDCE domain, which may enable VDDPE to be lower than VDDCE. However, a disadvantage is that this implementation may cause delay penalty to all signals going through level shifters inside memory, which may lead to timing degradation, such as memory access time and input pins setup time.